/*
 * Copyright (c) 2017 Qualcomm Atheros, Inc.
 * All Rights Reserved.
 * Qualcomm Atheros Confidential and Proprietary.
 */
#define BB_SM_HIST_0_REG_ADDR							0x107b4
#define BB_SM_HIST_0_SM_REC_MAC_TRIG_LSB				23
#define BB_SM_HIST_0_SM_REC_MAC_TRIG_MSB				25
#define BB_SM_HIST_0_SM_REC_MAC_TRIG_MASK				0x3800000
#define BB_SM_HIST_0_SM_REC_AGC_SEL_LSB					22							
#define BB_SM_HIST_0_SM_REC_AGC_SEL_MSB					22							
#define BB_SM_HIST_0_SM_REC_AGC_SEL_MASK				0x400000
#define BB_SM_HIST_0_SM_REC_DATA_NUM_LSB				18
#define BB_SM_HIST_0_SM_REC_DATA_NUM_MSB				21
#define BB_SM_HIST_0_SM_REC_DATA_NUM_MASK				0x3c0000
#define BB_SM_HIST_0_SM_REC_CHN_EN_LSB					14
#define BB_SM_HIST_0_SM_REC_CHN_EN_MSB					17
#define BB_SM_HIST_0_SM_REC_CHN_EN_MASK					0x3c000
#define BB_SM_HIST_0_SM_REC_PART_EN_LSB					4
#define BB_SM_HIST_0_SM_REC_PART_EN_MSB					13
#define BB_SM_HIST_0_SM_REC_PART_EN_MASK				0x3ff0
#define BB_SM_HIST_0_SM_REC_TIME_RES_LSB				2
#define BB_SM_HIST_0_SM_REC_TIME_RES_MSB				3
#define BB_SM_HIST_0_SM_REC_TIME_RES_MASK				0xc
#define BB_SM_HIST_0_SM_REC_MODE_LSB					1
#define BB_SM_HIST_0_SM_REC_MODE_MSB					1
#define BB_SM_HIST_0_SM_REC_MODE_MASK					0x2
#define BB_SM_HIST_0_SM_REC_EN_LSB						0
#define BB_SM_HIST_0_SM_REC_EN_MSB						0
#define BB_SM_HIST_0_SM_REC_EN_MASK						0x1


#define BB_SM_HIST_1_REG_ADDR							0x107b8
#define BB_SM_HIST_1_SM_REC_LAST_ADDR_LSB				24
#define BB_SM_HIST_1_SM_REC_LAST_ADDR_MSB				31
#define BB_SM_HIST_1_SM_REC_LAST_ADDR_MASK				0xff000000
#define BB_SM_HIST_1_SM_REC_SS_FORMAT_LSB				0
#define BB_SM_HIST_1_SM_REC_SS_FORMAT_MSB				1
#define BB_SM_HIST_1_SM_REC_SS_FORMAT_MASK				0x3


#define BB_RTT_CNTL_REG_ADDR								0x107bc
#define BB_RTT_CNTL_RTT_DO_FAC_INTERP_LSB					3
#define BB_RTT_CNTL_RTT_DO_FAC_INTERP_MSB					3
#define BB_RTT_CNTL_RTT_DO_FAC_INTERP_MASK					0x8
#define BB_RTT_CNTL_CF_RX_ERR_RST_RTT_LSB					2
#define BB_RTT_CNTL_CF_RX_ERR_RST_RTT_MSB					2
#define BB_RTT_CNTL_CF_RX_ERR_RST_RTT_MASK					0x4
#define BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_LSB		1
#define BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_MSB		1
#define BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_MASK		0x2
#define BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_LSB			0
#define BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_MSB			0
#define BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_MASK		0x1

#define BB_GAINS_MIN_OFFSETS_REG_ADDR						0x10008
#define BB_GAINS_MIN_OFFSETS_ENABLE_ANT_FAST_GC_CTRL_LSB	24
#define BB_GAINS_MIN_OFFSETS_ENABLE_ANT_FAST_GC_CTRL_MSB	24
#define BB_GAINS_MIN_OFFSETS_ENABLE_ANT_FAST_GC_CTRL_MASK	0x1000000
#define BB_GAINS_MIN_OFFSETS_USE_FIXED_GAIN_LSB				23
#define BB_GAINS_MIN_OFFSETS_USE_FIXED_GAIN_MSB				23
#define BB_GAINS_MIN_OFFSETS_USE_FIXED_GAIN_MASK			0x800000
#define BB_GAINS_MIN_OFFSETS_ENABLE_SRCH_START_GAIN_LSB		22
#define BB_GAINS_MIN_OFFSETS_ENABLE_SRCH_START_GAIN_MSB		22
#define BB_GAINS_MIN_OFFSETS_ENABLE_SRCH_START_GAIN_MASK	0x400000
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_PHY_ERR_LSB		21
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_PHY_ERR_MSB		21
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_PHY_ERR_MASK		0x200000
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_VOTING_LSB			20
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_VOTING_MSB			20
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_VOTING_MASK		0x100000
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_GC_LSB				19
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_GC_MSB				19
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_GC_MASK			0x80000
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_ENABLE_LSB			18
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_ENABLE_MSB			18
#define BB_GAINS_MIN_OFFSETS_CF_AGC_HIST_ENABLE_MASK		0x40000
#define BB_GAINS_MIN_OFFSETS_GAIN_FORCE_LSB					17
#define BB_GAINS_MIN_OFFSETS_GAIN_FORCE_MSB					17
#define BB_GAINS_MIN_OFFSETS_GAIN_FORCE_MASK				0x20000
#define BB_GAINS_MIN_OFFSETS_OFFSETC3_LSB					12
#define BB_GAINS_MIN_OFFSETS_OFFSETC3_MSB					16
#define BB_GAINS_MIN_OFFSETS_OFFSETC3_MASK					0x1f000
#define BB_GAINS_MIN_OFFSETS_OFFSETC2_LSB					7
#define BB_GAINS_MIN_OFFSETS_OFFSETC2_MSB					11
#define BB_GAINS_MIN_OFFSETS_OFFSETC2_MASK					0xf80
#define BB_GAINS_MIN_OFFSETS_OFFSETC1_LSB					0
#define BB_GAINS_MIN_OFFSETS_OFFSETC1_MSB					6
#define BB_GAINS_MIN_OFFSETS_OFFSETC1_MASK					0x7f

#define BB_CHANINFO_CTRL_REG_ADDR							0x10770
#define BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_LSB				8
#define BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_MSB				8
#define BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_MASK				0x100
#define BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB				0
#define BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB				0
#define BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK				0x1
#define BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_LSB			3
#define BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_MSB			3
#define BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_MASK			0x8


#define BB_FORCE_CLOCK_REG_ADDR								0x10754
#define BB_FORCE_CLOCK_ENA_REG_CLK_GATING_LSB				26
#define BB_FORCE_CLOCK_ENA_REG_CLK_GATING_MSB				26
#define BB_FORCE_CLOCK_ENA_REG_CLK_GATING_MASK				0x4000000

#define BB_CHN_TABLES_INTF_ADDR_REG_ADDR					0x10494
#define BB_CHN_TABLES_INTF_DATA_REG_ADDR					0x10498

#define BB_TXIQCAL_CONTROL_0_REG_ADDR						0x10a44
#define BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB			1
#define BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB			6
#define BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK			0x7e

#define BB_RXIQCAL_CONTROL_0_REG_ADDR						0x10b04



























































